湖人半导体（深圳）有限公司

K4T1G164QF-BCF7  FBGA84  封装  15+  SAMSUNG 品牌 

1. .JEDEC standard VDD = 1.8V ± 0.1V Power Supply
2. •VDDQ =1.8V ± 0.1V
3. •333MHz fCK for 667Mb/sec/pin, 400MHz fCK
4. for 800Mb/sec/pin•8 Banks
5. •Posted CAS•Programmable CASLatency: 3, 4, 5, 6
6. •Programmable Additive Latenc y: 0,1, 2, 3, 4, 5
7. •Write Latency(WL) = Read Latency(RL) -1
8. •Burst Length: 4 , 8(Interleave/nibblesequential)
9. •Programmable Sequential / Interleave Burst Mode
10. •Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
11. •Off-Chip Driver(OCD) Impedance Adjustment
12. •On Die Termination
13. •Special Function Support- 50ohm ODT - HighTemperature Self-Refresh rate enable•Average Refresh
14. Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
15. •All of products are Lead-Free,Halogen-Free, and RoHS compliantThe 1Gb DDR2 SDRAM is
16. organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device
17. .This synchronous device achieves high speed double-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for general applications
18. .The chip is designed to comply with the following key DDR2 SDRAM fea-tures such as
19. posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination
20. .All of the control and address inputs are synchronized with a pair of exter-nally
21. supplied differential clocks
22. . Inputs are latched at the crosspoint of dif-ferential clocks (CK rising and CK falling)
23. . All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source
24. synchronous fash-ion